Resume’ -- Dan Bezzant Principal Consultant at Prequel 1884 Paseo del Cajon Pleasanton, CA 94566-5911 email: dan@prequelinc.com Home Office: +1-925-426-7094 Fax: +1-925-485-4280 Residence: +1-925-426-1633 Technologies and Standards Device Experience South Bridge devices, PHY devices, clock distribution buffers and PLLs, CPLDs, Xilinx Virtex/Virtex 2 FPGA’s, VGA LCD controllers, PCI/PCMCIA bridges, PAL’s, T1 Framer IC’s, DDR SDRAM, QDR SRAM devices, nonvolatile storage IC’s, datacomm line interface IC’s. Microprocessor Experience Geode x86(Cyrix), Custom microprogrammed processors, as well as industry standard Intel 8051, Hitachi 6301(6800 compatible). Exposure to various other advanced processor architectures Electrical Interface Standards CMOS using mixed voltage level I/O cells. LVCMOS, LVPECL, HSTL, SSTL, HC, HCT, ACT logic families. Bus Standard Familiarity PCI, 10G Ethernet 802.3ae, ISA/PC104, SAS, ATA, IEEE 1394, PC Card(PCMCIA) Standard, VIP and VMI video busses Industry Initiatives ACPI, Microsoft/Intel PC Standards Hardware Development Skills ASIC and FPGA design using Verilog and VHDL Xilinx Virtex II and Virtex E FPGA design using ISE 6.X Test harness/testbench creation working off product specifications Test spec generation Test vector creation and debug ATE debug HDL Synthesis using Synplicity Synplify, Synopsys Design Compiler/Design Analyzer, XST. ECO netlist changes using Design Compiler. Timing constraint for synthesis script generation. Timing analysis and closure using ISE 6.X and Synopsys timing analysis tools. Interfacing with layout groups on floorplanning issues, pad design requirements, digital and analog PLL design requirements Backannotation of netlists and post-synthesis/post-layout regressions. Device padring planning for consistent board layout, voltage banking, power requirements, and EMI/ground bounce requirements Interfacing with FIB surgery services on FIB modifications to proto silicon Creation and execution of silicon validation plans Informal lab bench work on protos and formal prototype validation planning and execution Interfacing with silicon QA groups and process/electrical design groups on device latchup issues Interfacing with product engineering groups on customer returns and root cause analyses Low power design and ACPI compatible power management support in ASICS Thermal, EMC, and safety design issues Interface with industrial designers Experience Prequel, Inc. 1884 Paseo del Cajon Pleasanton, CA 94566 FPGA, ASIC, System Design Consultant 2/99-Present General FPGA and ASIC design consulting for clients as follows: ? Data Transit Corporation. – SAS Analyzer Creation of Xilinx Virtex II 2 million gate FPGA-based system to control and analyze SAS disk drive interface. Architecture, program planning and coordination, Verilog code development, simulation, synthesis, place and route, timing closure using Xilinx ISE tool flow, bench debug. ?Finisar Inc. – 10 Gigabit Ethernet Design Creation of Xilinx Virtex II 3 million gate FPGA-based system to perform 10 Gigabit Ethernet functions. Architecture, program planning and coordination, VHDL code development, MAC core selection and integration, simulation, synthesis, place and route, timing closure using Xilinx ISE tool flow. Extensive 2+ year assignment. ?National Semiconductor – ARM Evaluation PCB Design Creation of ATX form factor PCB for ARM evaluation. Featured 75 MHz SSRAM, various flash banks, standard PC busses and interfaces. ?National Semiconductor – South Bridge Verification Silicon verification of National cs5530 south bridge using National-proprietary scripting. Generation of test plan/procedures. ?Intermec – FPGA Prototyping Creation of Xilinx Virtex E FPGA design integrating an ARC VHDL-based 32 bit RISC with peripherals and digital section of a 2.4 GHz radio interface. ?Basis Communications – Application Consulting Advising end customer on behalf of Basis Communications concerning application of a Basis chip for Compact Flash interface in a telecomm application. ?O2 Micro – 1394 Training Presented training courses in the IEEE 1394 ‘Firewire™’ standard Advanced Resources 4900 Hopyard Ave. Pleasanton, CA 94566 Consultant 9/98-6/99 Validation Consultant ?9/98 – 6/99 On assignment at National Semiconductor’s Cyrix Division. Involved in validation of ATA and digital video input features of a chipset for use with Cyrix X86-compatible microprocessors. Wrote validation plans, procured necessary hardware for testing, wrote test scripts. Worked with design group and BIOS/driver developers to resolve any issues that came up in validation testing. ?Also on assignment 4/99-6/99 with National Semiconductor Israel’s MediaPC (Geode) single chip computer group. Validation and proto bringup of digital video input features for a MediaPC program 1394 Trade Association 2350 Mission College Blvd, Suite 350 Santa Clara, CA Managing Director 2/98-7/98 Spearheaded 1998 Annual 1394 Developer’s Conference – Headed the effort to put together a 3 day 78-speaker program for 700 attendees, on developing products using the IEEE 1394(‘Firewire’) interface. Set Up Association Office in California – Moved operations of the 1394 Trade Association to California. Did site screening and presentation, set up general banking and merchant accounts, selected CA lawyer to handle incorporation and other requirements to do business in California. Interviewed CPA’s, researched health plans, selected payroll service. Selected temporary employees for special projects. Advertised for staff, did candidate interviews, hired staff. Ran Operations -- Membership services, recruiting of members, contract review and negotiation, working with 18 member Board of Directors. Coordinating with PR contractor, press interviews, managing logistics of trade shows, organizing association quarterly meetings. Cirrus Logic, Inc. 3100 W. Warren Avenue, Fremont, CA 94538 Design Manager 7/92-1/98 Created 1394 Development Program – put together draft specification of 1394 interface IC. Created development plan resource requirements for a 1394 ASIC development, profiled the staff required and secured approvals, worked with an in-house recruiter to post openings and screen candidates, worked through offer processes. Worked team through top-level architecture and design partitioning. Helped Grow Successful PCMCIA Bridge Business – Responsible for design and tapeout of multiple PCI/Cardbus, PCI/PCMCIA, and ISA/PCMCIA bridge products in 0.9 and 0.6u standard cell technologies. Worked as individual contributor, team leader, and design manager on various product derivatives and performance enhancements. VHDL based methodology using Model Technology VHDL simulator, Synopsys for logic synthesis, Pathmill for static timing analysis. Involved with integration of custom cells into VHDL-based design, creating equivalent models for behavioral simulations. Extensive bench debug and verification using standard lab equipment, including bench tests of voltage and temperature extremes. Worked through a variety of production issues to keep product in high volume production. Developed new product concepts and specifications. Project scheduling, design coordination, verification planning and tracking, bug tracking and resolution for a variety of PCMCIA/Cardbus controller programs. Western Digital Imaging Mountain View, CA Principal Engineer 5/91-7/92 Project leader for Western Digital 90C26 LCD VGA controller Defined features with Marketing Task partitioning Development all the way through to first production parts ramp-up issue resolution including customer visits to work through problems. 0.9u schematic based standard cell design using AT&T foundry, libraries and Viewlogic/AT&T tool set Worked with analog design/layout group on I/O cellset specification for 3.3V operation at pins, interfaces and features for greyscale mapping RAM and on-board RAMDAC. Implemented pin mapping I/O connectivity test feature. Worked with technical writer to develop product datasheet. First silicon was sample-able on this program. Worked closely with IBM, NEC, and others to get product designed into notebook computers, including the first IBM Thinkpad. Verilink San Jose, CA Project Engineer 12/90-4/91 Tested modular T1 CSU/DSU telecommunications system Worked on resolving various circuit and product issues to prepare it for production Used combinations of different types of TTC and Scientific Atlanta telecommunications testers connected to various configurations of this modular system. Verified combinations of CSU and DSU interface cards within a system including V.35, EIA 422, and EIA 232D data interface functionality. Tested alarm reporting and translation/propagation. Tested bit error rates and error detection. Experimented with methods to reduce thermal profile. Reported problems to designers and worked with them on isolating causes and investigating solutions. ICL Datachecker Santa Clara, CA Sr. Design Engineer 9/89-12/90 Developed Components of Cash Register Created specifications from MRD for keyboard, flat panel vacuum flourescent display, and other cash register modules Researched possible solution providers and placed development RFQ’s to selected vendors Coordinated development of these products with third-party vendors and associated contractors, focusing on C-programmed 8051-based communication solutions between modules. Coordination included electrical and mechanical design, software development, integration, test, and release. (Resulting product: ICL 9520 cash register: still in use at some Albertsons, SaveMart, Eagle store locations) TAQ Communications Sr. Design Engineer 4/89-9/89 Design Work on Handheld T1 Testers Spent a few months at a former associate’s startup working on 8051-based handheld T1 testers utilizing Crystal T1 framer chips and Xilinx FPGA’s. Designed and added a peak voltage measurement circuit and a slip counter Designed digitally controlled battery powered circuits for tester’s LCD panel brightness and contrast. Designed front panel layout for handheld tester membrane keyboard DSC Communications Sr. Design Engineer 4/87-3/89 T3 to T1 Multiplexer/Demultiplexer and Switching Interface Worked as a member of a team developing a T3 interface to a T1-level switching fabric Was responsible for the T3 to T1 mux/demux section and an interface to a localized portion of the switching matrix Solution used proprietary T1 framer ASICs, proprietary M12 and M23 mux/demux ASICs, and a proprietary T1-to-switching-matrix ASIC. 6301(6800 derivative) processor based design for control of the framing and multiplexing ASICs as well as redundancy and loopback path controls. Implemented all glue logic, decodes, status latches in a 'handpacked' Xilinx FPGA. Followed product through from concept to protos and transfer to Texas for production engineering Memorex Communications Group Milpitas, CA Sr. Design Engineer 8/83-3/87 ASIC Group Lead Served as group leader of newly formed ASIC group at Memorex Coordinating two development teams while functioning as project leader on one. Coordinated efforts of a junior engineer and two experienced engineers on development of 3270 interface ASIC using a Unisys 2u CMOS process/library. Developed Strategic Video Terminal Product – Was responsible for development of a 2901/2910 bit-slice processor based 3270 compatible terminal product. Digital control of brightness, contrast, speaker volume, etc. Education B.S. Electrical Engineering, Brigham Young University, 1983, digital design emphasis M.S. Engineering Management, Santa Clara University, 1996. Technical emphasis: VLSI design Applicable Technical Training Xilinx Foundation ISE training, Synopsys Design Compiler, Design Analyzer(Beginning and Advanced Course), Pathmill static timing analysis course, Modelsim training Patents EP 0247092 A1 Displaying Characters with Selectable Attributes 5,634,075 Backward Compatibility for Plug and Play Systems 5,727,184 Method and Apparatus for Interfacing Between Peripherals of Multiple Formats and a Single System Bus 5,748,034 Combinational Logic Circuit, System, and Method for Eliminating Both Positive and Negative Glitches 5,796,981 Method and Apparatus for Providing Register Compatibility Between Non-Identical Integrated Circuits (Other patents pending) References Available Upon Request